1. Field of the Invention
The present invention generally relates to a semiconductor device. More particularly, the present invention relates to a memory device, and to a fabricating method and an operating method of the same.
2. Description of Related Art
A memory is a semiconductor device designed for storing info nation or data. As the functions of computer microprocessors become more and more powerful, programs and operations executed by software are increasing correspondingly. Consequentially, the demand for high storage capacity memories is getting more. Among various types of memory products, a non-volatile memory allows multiple-time data programming, reading and erasing operations, and the data stored therein can be retained even after the power to the memory is terminated. With these advantages, the non-volatile memory has become one of the most widely adopted memories for personal computers and electronic equipment.
Electrically programmable and erasable non-volatile memory technologies based on charge storage structures known as electrically erasable programmable read-only memory (EEPROM) and flash memory are used in a variety of modern applications. A typical flash memory is designed with an array of memory cells that can be independently programmed and read. The conventional flash memory cells store charge on a floating gate. When the memory is programmed, the electrons injected into the floating gate uniformly distributes in the polysilicon layer. However, when there are defects in the tunnel oxide layer under the polysilicon floating gate, the leakage is easily produced in the device. Hence, the reliability of the device is compromised.
Another type of the flash memory uses a charge-trapping structure, such as a layer of non-conductive SiN material, rather than the conductive gate material used in floating gate devices. When a charge-trapping cell is programmed, the charge is trapped and does not move through the non-conductive layer. The charge is retained by the charge-trapping layer until the cell is erased, retaining the data state without continuously applied electrical power. In addition, the electrons are only stored in a portion of the charge-trapping layer over the channel region adjacent to a source or drain region when the device is programmed. Because the charge does not move through the non-conductive charge-trapping layer, the charge can be localized on different charge-trapping sites.
Conventionally, there are two separated storage sites in a memory cell with planar channel, which is considered as a 2-bit-per-cell memory device shown in FIG. 1. The only way for increasing storage density is achieved by scaling the cell length of the planar channel cell. When the cell length is scaled down, the planar channel cell with demanded shallow junctions is prone to worse programming disturbance and higher resistance of the source and drain regions. As the cell is miniaturized, electrons stored in adjacent two bits are liable to merge due to the shrunk length, so that the second bit effect is getting worse. Moreover, as shown in FIG. 1, in the programming progress of channel hot electron injection (CHEI), redirection collision is required to send the electron toward a charge-trapping site 100 in the storage layer. Such redirection affects injection efficiency, and thereby higher voltage of about 7.5˜11.5V is required for the Vg applied to the gate.